A power semiconductor device includes a Schottky diode, a pn diode, an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the like which use a silicon carbide (SiC) substrate. In these power semiconductor devices, various termination structures are introduced in order to prevent an electric field from concentrating on a pn junction portion in the SiC substrate. The termination structure includes a JTE (Junction Termination Extension) structure (for example, see Non-Patent Document 1).
The JTE structure has a feature that it can easily be formed by ion implantation. Moreover, the JTE structure also has a feature that it can easily be designed because a carrier concentration of a JTE region is preferably designed in order to cause the JTE region to be perfectly depleted in a dielectric breakdown.
Referring to a semiconductor device having the JTE structure (which will be hereinafter referred to as a “device” in some cases), the following techniques are proposed in order to reduce an electric field intensity on a surface of the JTE region. For example, in Patent Document 1, the technique for giving a concentration gradient to a JTE region is proposed. In Patent Document 2, moreover, there is proposed the technique for covering a pn junction and a JTE region with a third layer. By these techniques, a semiconductor device having a high withstand voltage is attempted to be implemented.